Technical Field
The present disclosure generally relates to the field of semiconductor packaging and methods for assembling same.
Description of the Related Art
Semiconductor die are packaged to protect the die from the external environment and to provide mechanical support. For manufacturers of semiconductor devices, there is a continuing pressure to increase the size of the packages. One response to this pressure has been the development of chip scale and wafer level packaging. These are packages that have a footprint that is very close to the actual area of the semiconductor die. Chip scale packages are generally direct surface mountable, using, e.g., ball grid arrays (BGA) and flip chip configurations.
Another response has been to assemble system-in-packages (SiP), which include multiple semiconductor dice or chips enclosed in a single package body. For instance, micro-electromechanical systems (MEMS) packages often include a MEMS die and an application-specific integrated circuit (ASIC) die coupled to a substrate in a side by side configuration. The ASIC die is electrically coupled to the MEMS die and to the substrate, such as by conductive wires.
To further reduce package size, the MEMS die and ASIC die may be stacked on each other over the substrate. In general, the larger die would be on the bottom and coupled to the substrate. That is, a stack may include an ASIC coupled to the substrate and a MEMS die, which is smaller than the ASIC die, is coupled to an upper surface of the MEMS die.
Conductive through vias to couple the MEMS and ASIC dice together are often utilized to further reduce package sizes. Conductive through vias, however, typically require expensive processing techniques. Thus, there remains a continued desire to provide smaller packages at reduced costs.